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integrated silicon solution, inc. ? 1-800-379-4774 1 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? copyright ? 2004 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 65,536 bit/32,768 bit 2-wire serial cmos eeprom advanced information january 2004 description the is24c32a and is24c64a/b are electrically erasable prom devices that use the standard 2- wire interface for communications. the is24c32a and is24c64a/b contain a memory array of 32k- bits (4k x 8) and 64k-bits (8k x 8), respectively. each device is organized into 32 byte pages for page write mode. this eeprom is offered in wide operating volt- ages of 1.8v to 5.5v (is24cxx-2) and 2.5v to 5.5v (is24cxx-3) to be compatible with most application voltages. issi designed this device family to be a practical, low-power 2-wire eeprom solution. the devices are available in 8-pin pdip, 8-pin soic and 8-pin tssop packages. the is24c32a/64a/64b maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. the simple bus consists of the serial clock wire (scl) and the serial data wire (sda). using the bus, a master device such as a microcontroller is usually connected to one or more slave devices such as this device. the bit stream over the sda line includes a series of bytes, which identifies a particular slave device, an instruction, an address within that slave device, and a series of data, if appropriate. the is24c32a/64a/64b has a write protect pin (wp) to allow blocking of any write instruction transmitted over the bus. features ? two-wire serial interface ?bi-directional data transfer protocol 400 khz (i 2 c protocol) compatibility low power cmos technology ?standby current less than 6 a (5.0v) ?read current less than 2 ma (5.0v) ?write current less than 3 ma (5.0v) flexible voltage operation ?vcc = 1.8v to 5.5v for ?2 version ?vcc = 2.5v to 5.5v for ?3 version hardware data protection ?is24c32a/64a: wp protects entire array ?is24c64b: wp protects top quarter of array sequential read feature filtered inputs for noise suppression 8-pin pdip, 8-pin soic and 8-pin tssop packages self time write cycle with auto clear 5 ms @ 2.5v organization: ?is24c32a: 4kx8 (128 pages of 32 bytes) ?is24c64a/b: 8kx8 (256 pages of 32 bytes) 32 byte page write buffer high reliability ?endurance: 1,000,000 cycles ?data retention: 100 years commercial and industrial temperature ranges
2 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control eeprom array y decoder data register clock di/o ack 8 5 6 7 4 gnd wp scl sda vcc nmos 1 2 3 a2 a1 a0 pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. the sda bus requires a pullup resistor to vcc. a0, a1, a2 the a0, a1 and a2 are the device address inputs that are hardwired or left not connected for hardware compatibility pin configuration 8-pin dip, soic, and tssop 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda functional block diagram with the 24c16. when pins are hardwired, as many as eight 32k/64k devices may be addressed on a single bus system. when the pins are not hardwired, the default values of a0, a1, and a2 are zero. wp wp is the write protect pin. with is24c32a/64a, if the wp pin is tied to vcc, the entire array becomes write protected (read only). with is24c64b, if wp is tied to vcc, the top quarter of the array (1800h-1fffh) becomes write protected. when wp is tied to gnd or left floating, normal read/write operations are allowed to the device.
integrated silicon solution, inc. ? 1-800-379-4774 3 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? device operation is24c32a/64a/64b features serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-wire bus the two-wire bus is defined as a serial data line (sda), and a serial clock line (scl). the protocol defines any device that sends data onto the sda bus as a transmitter, and the receiving devices as a receiver. the bus is controlled by a master device that generates the scl, controls the bus access, and generates the stop and start conditions. the is24c32a/64a/64b is the slave device on the bus. the bus protocol: ? data transfer may be initiated only when the bus is not busy ? during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. the state of the data line represents valid data after a start condition. the data line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. start condition the start condition precedes all commands to the device and is defined as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the is24c32a/64a/64b contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. the reset is caused when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line, which may cycle the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode power consumption is reduced in standby mode. the is24c32a/64a/64b will enter standby mode: a) at power- up, and remain in it until scl or sda toggles; b) following the stop signal if a no write operation is initiated; or c) following any internal write operation.
4 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? write operation byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w set to zero) to the slave device. after the slave generates an ack, the master sends the two byte address that is to be written into the address pointer of the is24c32a/64a/ 64b. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the is24c32a/64a/64b acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the is24c 32a/64a/64b is capable of 32-byte page-write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to 31 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is incremented from the last byte of a page, it returns to the first byte of that page. if the m aster device should transmit more than 32 bytes prior to issuing the stop condition, the address counter will ?roll over,? and the previously written data will be overwritten. once all 32 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the is24c 32a/64a/64b in a si ngle write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the is24c32a/64a/64b initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the is24c32a/64a/ 64b has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave devices it is requesting. the slave (fig. 5) address is 8 bits. the four most significant bits of the address are fixed as 1010 for the is2432a/64a/64b. the next three bits of the slave address are a0, a1, and a2, and are used in comparison with the hard-wired input values on the a0, a1, and a2 pins. up to eight is24c32a/64a/64b units may share the 2-wire bus. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master transmits the start condition and slave address byte (fig. 5), the appropriate 2-wire slave (eg.is24c64a) will respond with ack on the sda line. the slave will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the selected eeprom then prepares for a read or write operation by monitoring the bus.
integrated silicon solution, inc. ? 1-800-379-4774 5 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? read operation read operations are initiated in the same manner as write operations, except that the (r/ w ) bit of the slave address is set to ?1?. there are three read operation options: current address read, random address read and sequential read. current address read the is24c32a/64a/64b contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/ w bit set to ?1?), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the is24c32a/64a/64b discontinues transmission. if 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the is24c32a/64a/64b acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the eeprom then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the is24c32a/64a/64b sends initial byte sequence, the master device now responds with an ack indicating it requires additional data from the is24c32a/64a/64b. the eeprom continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of 8191 for is24c64a/b or 4095 for is24c32a (depending on the device) is reached, the address counter ?rolls over? to address 0, and the device continues to output data. (refer to figure 10. sequential read diagram).
6 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? scl sda master transmitter/ receiver is24c32a/64a/64b vcc figure 1. typical system bus configuration t aa data output from transmitter scl from master data output from receiver 189 ack t aa figure 2. output acknowledge stop condition scl sda start condition figure 3. start and stop conditions
integrated silicon solution, inc. ? 1-800-379-4774 7 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? figure 5. slave address figure 4. data validity protocol scl sda data stable data stable data change 7 bit 43 1 2 5 60 r/ w a0 a1 a2 0 1 0 1 figure 6. byte write figure 7. page write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/ w a c k a c k a c k data device address word address a c k word address * = don't care bits # = don't care bit for 24c32a * ** # sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) word address (n) device address s t o p a c k data (n+31) r/ w a c k word address (n) * = don't care bits # = don't care bit for 24c32a * ** #
8 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? figure 8. current address read figure 9. random address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w sda bus activity a c k a c k a c k data n word address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/ w a c k word address (n) * = don't care bits # = don't care bit for 24c32a * ** # figure 10. sequential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
integrated silicon solution, inc. ? 1-800-379-4774 9 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage ?0.5 to +6.25 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (is24c64a/b-2 and is24c32a-2) range ambient temperature v cc commercial 0c to +70c 1.8v to 5.5v industrial ?40c to +85c 1.8v to 5.5v capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 5.0v. operating range (is24c64a/b-3 and is24c32a-3) range ambient temperature v cc commercial 0c to +70c 2.5v to 5.5v industrial ?40c to +85c 2.5v to 5.5v
10 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? ac waveforms figure 11. bus timing t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp 8th bit ack word n stop condition start condition t wr scl sda figure 12. write cycle timing
integrated silicon solution, inc. ? 1-800-379-4774 11 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? dc electrical characteristics commercial (t a = 0 o c to +70 o c), industrial (t a = -40 o c to +85 o c) symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 1.8v, i ol = 0.15 ma ? 0.2 v v ol 2 output low voltage v cc = 2.5v, i ol = 3 ma ? 0.4 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?1.0 v cc x 0.3 v i li input leakage current v in = v cc max. ? 3 a i lo output leakage current ? 3 a power supply characteristics commercial (t a = 0 o c to +70 o c), industrial (t a = -40 o c to +85 o c) symbol parameter test conditions min. max. unit i cc 1 vcc operating current read at 400 khz (vcc = 5v) ? 2.0 ma i cc 2 vcc operating current write at 400 khz (vcc = 5v) ? 3.0 ma i sb 1 standby current vcc = 1.8v ? 1 a i sb 2 standby current vcc = 2.5v ? 2 a i sb 3 standby current vcc = 5.0 v ? 6 a notes: v il min and v ih max are reference only and are not tested. ac electrical characteristics commercial (t a = 0 o c to +70 o c) industrial (t a = -40 o c to +85 o c) 1.8v-5.5v 2.5v-5.5v 4.5v-5.5v symbol parameter min. max. min. max. min. max. unit f scl scl clock frequency 0 100 0 400 0 1000 khz t noise suppression time (1) ? 100 ? 50 ? 50 ns t low clock low period 4.7 ? 1.2 ? 0.6 ? s t high clock high period 4 ? 0.6 ? 0.4 ? s t buf bus free time before new transmission (1) 4.7 ? 1.2 ? 0.5 ? s t su:sta start condition setup time 4 ? 0.6 ? 0.25 ? s t su:sto stop condition setup time 4 ? 0.6 ? 0.25 ? s t hd:sta start condition hold time 4 ? 0.6 ? 0.25 ? s t hd:sto stop condition hold time 4 ? 0.6 ? 0.25 ? s t su:dat data in setup time 100 ? 100 ? 100 ? ns t hd:dat data in hold time 0 ? 0 ? 0 ? ns t su : wp wp pin setup time 4 ? 0.6 ? 0.6 ? s t hd : wp wp pin hold time 4.7 ? 1.2 ? 1.2 ? s t dh data out hold time (scl low to sda data out change) 100 ? 50 ? 50 ? ns t aa clock to output ( scl low to sda data out valid) 100 3500 50 900 50 400 ns t r scl and sda rise time (1) ? 1000 ? 300 ? 300 ns t f scl and sda fall time (1) ? 300 ? 300 ? 100 ns t wr write cycle time ? 10 ? 10 ? 5 ms
12 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00a 01/26/04 is24c32a is24c64a/b issi ? ordering information commercial range: 0c to +70c voltage frequency range part number package 100 khz 1.8v is24c32a-2p 300-mil plastic dip to 5.5v is24c32a-2g sm all outline (jedec std) 100 khz 1.8v is24c64a-2p 300-mil plastic dip to 5.5v is24c64a-2g sm all outline (jedec std) 100 khz 1.8v is24c64b-2p 300-mil plastic dip to 5.5v is24c64b-2g sm all outline (jedec std) 400 khz 2.5v is24c32a-3p 300-mil plastic dip to 5.5v is24c32a-3g sm all outline (jedec std) 400 khz 2.5v is24c64a-3p 300-mil plastic dip to 5.5v is24c64a-3g sm all outline (jedec std) 400 khz 2.5v is24c64b-3p 300-mil plastic dip to 5.5v is24c64b-3g sm all outline (jedec std) ordering information industrial range: ?40c to +85c voltage frequency range part number package 100 khz 1.8v is24c32a-2pi 300-mil plastic dip to 5.5v i s24c32a-2gi sm all outline (jedec std) 100 khz 1.8v is24c64a-2pi 300-mil plastic dip to 5.5v i s24c64a-2gi sm all outline (jedec std) 100 khz 1.8v is24c64b-2pi 300-mil plastic dip to 5.5v i s24c64b-2gi sm all outline (jedec std) 400 khz 2.5v is24c32a-3pi 300-mil plastic dip to 5.5v i s24c32a-3gi sm all outline (jedec std) 400 khz 2.5v is24c64a-3pi 300-mil plastic dip to 5.5v i s24c64a-3gi sm all outline (jedec std) 400 khz 2.5v is24c64b-3pi 300-mil plastic dip to 5.5v i s24c64b-3gi sm all outline (jedec std)

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